The term RISC dates from about 1980.[16] Before then, there was some knowledge that simpler computers can be effective (e.g., John Cocke at IBM Research), but the design principles were not widely described. Simple, effective computers have always been of academic interest, and resulted in the RISC instruction set DLX for the first edition of Computer Architecture: A Quantitative Approach in 1990 of which David Patterson was a co-author, and he later participated in the RISC-V origination. DLX was intended for educational use; academics and hobbyists implemented it using field-programmable gate arrays, but it was never truly intended for commercial deployment. ARM CPUs, versions 2 and earlier, had a public-domain instruction set and are still supported by the GNU Compiler Collection (GCC), a popular free-software compiler. Three open-source cores exist for this ISA, but were never manufactured.[17][18] OpenRISC is an open-source ISA based on DLX, with associated RISC designs, and is fully supported with GCC and Linux implementations, although it too has few commercial implementations.
As of 2019[update], RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the trademarked compatibility logo.[23]
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The existing control and status register definitions support RISC-V's error and memory exceptions, and a small number of interrupts. For systems with more interrupts, the specification also defines an interrupt controller. Interrupts always start at the highest-privileged machine level, and the control registers of each level have explicit forwarding bits to route interrupts to less-privileged code. For example, the hypervisor need not include software that executes on each interrupt to forward an interrupt to an operating system. Instead, on set-up, it can set bits to forward the interrupt.[2] 2ff7e9595c
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